The apparatus of the present invention generally relates to data processing systems and more particularly to a priority network for providing transfer cycles over a common bus coupling a plurality of units in such system.
The apparatus of the present invention is an improvement to the priority logic described in U.S. Pat. No. 4,030,075, issued on June 14, 1977, which patent is incorporated herein by reference. Such priority logic included in the priority network of such patent application is distributed in each of the units coupled to the common bus so as to enable priority determination and thereby the granting of a bus cycle to the highest priority requesting unit without the need for a bus monitor for example in a central processor which may be one of the units coupled to the bus. Each such priority logic includes three bistable elements, one of which indicates an internal request for use of the bus, another of which indicates on the bus that an internal request has been made, and a further one is provided to indicate that a bus cycle has been granted for this unit. Only one such unit's priority logic may have its so-called bistable element indicate that a bus cycle has been granted. The priority logic in more than one unit may have their so-called request bistable elements set to indicate that they desire bus cycles. Typically, the unit transferring information to another unit receives a response. Such response may either be a signal indicating that the information transferred has been accepted (an ACK signal), that the information transferred has not been accepted (a NACK signal), or a signal indicating that the information has not been accepted by the receiving unit but that such receiving unit will be enabled to so receive such information possibly during the next bus cycle (a WAIT signal). In response to either of these signals, it has been shown in such aforementioned patent that the so-called grant bistable element which has been set, may be reset so that each of the units on the bus may again in parallel attempt to gain access to the bus, thereby avoiding a situation where one unit which had previously been granted access to the bus is unable to gain such access until its receiving unit responds by indicating it has received such information. In such aforementioned patent, it was shown that the so-called ACK or NACK signals would also cause the so-called request bistable element to be reset or cleared. However in so resetting such request bistable element it is important that only the unit which had its grant bistable element set have its request bistable element reset. Otherwise, each of the request bistable elements in each of the units would be reset. This would then require that each of such units have its so-called request bistable element set again. In order to avoid such operation, it was necessary to include logic by which the unit so setting its so-called grant bistable element retain a history of such action. This required additional logic in the system and, accordingly, it was considered desirable to eliminate such excess logic thereby reducing the space and power requirements in the system while still maintaining priority logic which was distributed, asynchronous in nature and which retained the speed required of the system.
Accordingly, it is a primary object of the present invention to provide improved priority logic for use in a data processing system in which a plurality of units are coupled over a common electrical bus.